PDN Target Impedance (FPGA)

Calculate target Power Delivery Network (PDN) impedance and minimum bulk capacitance.

PDN Target Impedance Graph

FPGA Core Power Specs

Target Impedance (Ztarget)

-- mΩ

Required Bulk Cap (Cbulk)

-- μF
Allowed Ripple
-- mV

Maintain impedance ≤ Ztarget up to the Target Bandwidth to prevent rail droop.

Designing an FPGA Power Delivery Network

Field Programmable Gate Arrays (FPGAs) can rapidly switch thousands of internal logic gates simultaneously, creating massive, near-instantaneous demands for current. This sudden current draw (transient step, ΔI) can cause the core voltage rail to droop or ring, potentially causing logical errors if it exceeds the allowable ripple bounds.

The goal of PDN design is to keep the impedance of the power rail below a specific Target Impedance (Ztarget) across a broad frequency band. If the impedance is kept low, any sudden surge in current demand will only generate a small, acceptable voltage ripple (V = I × Z).

The calculation is simple: Ztarget = (Vcore × Ripple%) / ΔI. Meeting this target impedance usually requires a carefully designed network of bulk capacitors, mid-frequency decoupling ceramics, and high-frequency on-die capacitance.