PLL / MMCM Clock Synthesizer Calculator

Find optimal multiplier and divider settings to synthesize any target clock frequency from a reference oscillator

Clock Configuration

MHz
Common: 10 · 12 · 25 · 33.33 · 50 · 100 · 125 · 200 MHz
MHz
Common: 25 · 74.25 · 100 · 148.5 · 200 · 300 · 400 MHz
Xilinx 7-Series MMCM: VCO 600–1200 MHz · M: 2–64 · D: 1–106 · O: 1–128 · PFD ≥ 10 MHz
Best Match
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Frequency Error
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VCO Frequency
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Valid Configurations Found
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All Valid Configurations

Sorted by lowest frequency error. FOUT = FREF × M / (D × O), where VCO = FREF × M / D must stay within the valid range.

# M D O FOUT (MHz) VCO (MHz) Error Error (ppm)
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Understanding PLL / MMCM Clock Synthesis

FPGAs use Phase-Locked Loops (PLLs) or Mixed-Mode Clock Managers (MMCMs) to generate precise clock frequencies from a reference oscillator. The output frequency is determined by three integer parameters:

FOUT = FREF × M / (D × O)

VCO Constraints

The VCO frequency (FREF × M / D) must stay within the FPGA family's valid range. Operating outside this range causes clock instability, jitter, or failure to lock.

Phase Detector Frequency

The PFD frequency (FREF / D) should remain above the minimum specified by the FPGA vendor (typically ≥10 MHz for Xilinx) to ensure reliable lock acquisition and low jitter.